1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly to a semiconductor memory device composed of an SRAM (static random access memory).
2. Description of the Related Art
SGT (surrounding gate transistor) technologies are known as measures for attaining higher levels of integration and performance in semiconductor devices (disclosed for example in Unexamined Japanese Patent Application KOKAI Publication No. H2-188966). SGTs are vertical gate transistors in which a columnar semiconductor layer is formed on the surface of a semiconductor substrate and a gate is formed on the sidewall of the columnar semiconductor layer to surround it. In such an SGT, the drain, gate, and source are arranged in the direction orthogonal to the substrate. Therefore, the SGT has a significantly reduced occupying area compared with conventional planar transistors.
With the increasingly strong demands in recent years for large capacity SRAMs installed in LSIs (large-scale integrated circuits), it is desired to attain an SRAM having a small cell area with the use of SGTs. It is possible in an SRAM using SGTs, to reduce the SRAM cell area compared with SRAMs composed of conventional planar transistors by exploiting characteristics of vertical transistors.
FIG. 17A is a plan view of an E/R 4T-SRAM composed of four SGTs and two load resistance elements shown in an embodiment of Unexamined Japanese Patent Application KOKAI Publication No. H2-188966 and FIG. 17B is a cross-sectional view at the section line A-A′ in FIG. 17A.
In FIG. 17A and FIG. 17B, this SRAM cell is composed of access transistors formed by two columnar silicon layers (701a, 701b) and used for accessing the memory cell, driver transistors formed by two columnar silicon layers (702a, 702b) and used for driving the memory cell to read/write data, and two load resistance elements (Ra7, Rb7) formed by polysilicon wires. Lower diffusion layers (707a, 707b, 707) are formed at the bottoms of the columnar silicon layers and an upper diffusion layer 708 is formed in the upper part of them. Gate electrodes (706a to 706c) are formed around the columnar silicon layers. BL7 and BLB7 are bit lines and WL7 is a word line, Vcc7 is a power supply potential wire, and Vss7 is a ground potential wire. Furthermore, Ma7 and Mb7 are memory nodes formed by wiring layers and used for storing data.
The above-described conventional SRAM cell is formed of three diffusion layers (707a, 707b and 707). Therefore, reduction of cell area is limited by the width of each diffusion layer and distances between diffusion layers.